In many types of logic circuits, logic networks which utilize both clock and data signals are often used. These networks may rely on close synchronization of the signals in order to operate properly. The data and clock signals are designed to arrive at particular logic gates at precise times. If a clock or data signal is expected at a particular logic gate at a precise time, and that clock or data signal arrives too early or too late, incongruous results may occur.
The design of logic circuitry is becoming increasingly complex, and yet the desire for increased speeds of operation and larger band widths still remain. Thus, the timing analysis of the logic networks must become more accurate and therefore any excessive pessimism in the design of the circuits should be removed. As used here, excessive pessimism refers to the use of conservative tolerances (or wide margins), so conservative or wide that they are not necessary for proper operation of the circuit. Just why the tolerances are too conservative will become clear below.
A phase locked loop is often used to control the arrival times of clock signals to latches and other clocked elements in some portion of a synchronous system. The phase locked loop compensates for process and environmental variations in the chip and thus reduces the variation in the clock arrival times between different portions of the system whose clocks are controlled by different phase locked loops. However, statistical variation can still cause significant differences across different branches of a clock tree sourced by a phase locked loop. The branch of the clock tree which supplies the feedback signal to the phase locked loop will be better synchronized with the data signals outside the influence of the phase locked loop, since the branch of the clock tree in the feedback loop exhibits variation only due to the jitter and phase error of the phase locked loop and not the additional variation across the clock tree. Thus, external synchronization will be better or worse depending on how much of the clock tree branch is in common with the feedback path which controls the phase locked loop. Current static timing analysis techniques do not account for this improved synchronization.
For example, U.S. Pat. No. 4,924,430 discloses a method of static timing analysis which accounts for various factors; such as wire capacitance and temperature. However, this method does not consider that the clock or data signals may share a common path. The method of U.S. Pat. No. 5,636,372 does account for the fact that signals in a circuit may share a common path. This method identifies signals which share common paths and merges their arrival times. These times are used to determine the slack, that is the difference between the actual arrival time of a signal at a point and the time the signal is required to arrive, for various points throughout the circuit. But here again there is no accounting that the feedback path will be more closely synchronized with the reference clock.
To take advantage of this improved synchronization requires a form of common path pessimism removal quite different from the prior art. More particularly, because of the accurate synchronization between the reference clock and the timing in the feedback path of the phase locked loop, little or no timing tolerance is required in that path. As a circuit location is removed further and further from the direct feedback path more and more timing tolerance is required. In the absence of this recognition, circuit designs exhibit common path pessimism in the feedback path and paths common thereto which can be safely removed in order to increase the efficiency of the circuit.
It is therefore an object of the invention to provide a method of removing excessive common path pessimism in timing analysis when analyzing circuits containing one or more phase locked loops, or other similar circuitry which is designed to align a clock distribution tree with a reference clock by comparing a clock signal fed back from a branch of the distribution tree with the reference clock and making delay adjustments in the arrival time at the phase locked loop output at the root of the distribution tree to realign the distributed clock with the reference clock.